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Verilog/SystemC VCS cosim


The major steps involved to create a simulation for each of these design scenarios are:

1. Analyze the SystemC and Verilog modules from the bottom of the design to the top.


2. For Verilog designs containing SystemC modules:
- Use the syscan file.cpp:model command to analyze SystemC modules used in the Verilog domain.
- Use the syscan f.cpp... command to compile other SystemC modules in the design.
- Use the vlogan command to analyze Verilog files.
- Use the vcs -sysc command to build the simulation.



3. For SystemC designs containing Verilog modules:
- Use the vlogan -sc_model command to analyze Verilog files containing modules used in the SystemC domain.
- Use the syscan f.cpp... command to compile SystemC files.
- Use the syscsim command to build the simulation.



Using the VCS / SystemC Cosimulation Interface Note:
There are examples of Verilog instantiated in SystemC, and  SystemC instantiated in Verilog, in the $VCS_HOME/doc/examples/osci_dki directory.
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